PCBSync Engineering Tools
| Layer | Type | Thickness | Material |
|---|
| Parameter | Standard | Advanced | Premium/HDI |
|---|---|---|---|
| Min Trace Width | 6 mil | 4 mil | 3 mil |
| Min Space | 6 mil | 4 mil | 3 mil |
| Min Hole Size | 0.3 mm | 0.2 mm | 0.1 mm |
| Min Annular Ring | 6 mil | 4 mil | 3 mil |
| Aspect Ratio | 8:1 | 10:1 | 12:1 |
Place components in this order: connectors at board edges, power supply components near input, high-speed ICs centrally, analog/RF sections isolated, and decoupling caps as close as possible to IC power pins.
Use solid ground planes on 4+ layer boards. Keep power and ground planes adjacent for maximum decoupling. Avoid splitting ground planes unless necessary for isolation.
Route high-speed signals on layers adjacent to ground planes. Match trace lengths for differential pairs within 5 mils. Keep signals away from board edges and splits in reference planes.
Add thermal vias under high-power components (array of 0.3mm vias). Use exposed copper pads for heat dissipation. Consider 2oz copper for high-current paths.
Route clock signals as short as possible. Use guard traces or ground pours around sensitive signals. Place filter components at I/O connectors. Add stitching vias around board periphery.
Use via-in-pad only when necessary (requires filled and plated vias). For standard designs, keep vias away from pads by at least 10 mils. Use via stitching for ground connections every 1/20 wavelength for RF.
Separate analog and digital grounds, connect at single point near power entry. Use star grounding for precision analog. Keep digital signals away from analog inputs. Shield sensitive traces with ground.
Run DRC before every release. Check minimum clearances, annular rings, and silk-to-pad spacing. Verify drill-to-copper clearances. Test impedance-controlled nets against stackup.
Add 5mm rails with tooling holes (min 3.2mm). Use V-scoring for straight edges, tab routing for complex shapes. Add fiducials on panel and individual boards. Include breakaway tabs every 50-75mm.
Minimum PTH: 0.2mm finished. Keep aspect ratio ≤10:1. Add 0.1mm to finished hole size for tolerance. Annular ring minimum: 0.15mm (standard) or 0.1mm (advanced). Slot minimum width: 0.5mm.
Min trace: 0.1mm (4mil) standard. Maintain uniform copper balance (40-60% per layer). Add copper thieving in sparse areas. Teardrop connections improve yield. Avoid acute angles <45°.
Minimum solder mask dam: 0.1mm. Solder mask expansion from pad: 0.05mm typical. Define solder mask clearance for BGA pads (SMD vs NSMD). Specify mask over via requirements clearly.
Minimum line width: 0.15mm. Minimum text height: 0.8mm. Keep 0.15mm clearance from pads. Use vector fonts, not TrueType. Include reference designators, polarity marks, pin 1 indicators, and assembly revision.
Include: Gerber RS-274X or Gerber X2, NC drill files (Excellon), IPC-D-356 netlist, stackup drawing, fab drawing with notes, assembly drawings, BOM, and pick-and-place centroid file.
Keep copper 0.25mm from board edge (routed) or 0.4mm (V-scored). Components minimum 2mm from edge. Via minimum 0.5mm from edge. Add keepout zones under mounting hardware.
Orient similar components consistently. Group SMD on one side if possible. Provide adequate spacing for rework (2mm between ICs). Add test points for critical signals. Include polarity indicators for all polarized components.